← IGCSE Computer Science Paper 1

Execute stage

The stage of the fetch-decode-execute cycle where the decoded instruction is carried out, e.g. fetching data, calculating in the ALU, storing in the ACC, or changing the PC.

Part of: IGCSE Computer Science 0478 — 3.1 Computer Architecture — Module 23

Understanding Execute stage in IGCSE Computer Science Paper 1

What it does: The operand's address goes into the MAR, the address bus carries it to RAM, and the data returns through the data bus into the MDR. The ACC holds the results of calculations made by the ALU in the execute stage. Execute is the stage where the CPU actually does what the instruction says. Copying the instruction from RAM into the MDR is part of the fetch stage. The ALU does arithmetic and logic. The control unit only directs and coordinates what happens. The address is sent along the address bus, the control bus sends a read signal, and the data comes back along the data bus.

Common mistakes: The ALU adds the operand to the ACC only when the decoded opcode is ADD. A JMP instruction changes the PC instead. The line should be IF opcode = ADD THEN. LDA loads data from address 40, so the address goes into the MAR to read RAM. Putting it in the PC would make the CPU jump instead. It should be MAR <- 40.

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This module's key terms are also in a printable crossword (Modules 228–239) and word search (Modules 218–239).

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Learning
Duo
What happens in the execute stage of the fetch-decode-execute cycle?
The decoded instruction is carried outThe instruction is copied from RAM into the MDR
Matches
Execute stage: the instruction is copied from the PC into the MAR
↓
This describes the start of the fetch stage, not execute. In execute the decoded instruction is carried out, e.g. an ALU calculation or a change to the PC.
Applying
Meanings
Term
execute
Meaning
The stage of the fetch-decode-execute cycle where the decoded instruction is carried out, e.g. fetching data, calculating in the ALU, storing in the ACC, or changing the PC.
Practice
EXECUTE ADD 7
Testing
Gaps
Execute ADD: ACC ← ACC +
Check Answer
Spots
1IF opcode = JMP THEN
2 ALU adds operand to ACC

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Quick Questions

1. What happens in the execute stage of the fetch-decode-execute cycle?
A. The decoded instruction is carried out ✓
B. The instruction is copied from RAM into the MDR
Execute is the stage where the CPU actually does what the instruction says. Copying the instruction from RAM into the MDR is part of the fetch stage.
2. Which part of the CPU performs a calculation such as ADD during the execute stage?
A. The control unit
B. The ALU ✓
The ALU does arithmetic and logic. The control unit only directs and coordinates what happens.
3. Where is the result of an ALU calculation usually held straight after it is worked out?
A. In the accumulator (ACC) ✓
B. In the program counter (PC)
The ACC holds the results of calculations done by the ALU. The PC only holds the address of the next instruction.
4. An instruction needs a data value that is stored in RAM. What happens in the execute stage?
A. The data is fetched from RAM using the buses ✓
B. The data is fetched from RAM without using any buses
The address is sent along the address bus, the control bus sends a read signal, and the data comes back along the data bus.
5. What does a jump instruction do when it is executed?
A. It clears the value in the ACC
B. It changes the value in the PC ✓
A jump puts a new address into the PC, so the next instruction fetched comes from that address instead of the next one in order.

Match the Pairs

ACC ← ACC + MDR → The ALU adds the data fetched from memory to the value in the accumulator, and the result is held in the ACC
PC ← 20 → A jump instruction is executed, so the program counter is changed and the next fetch comes from address 20
During execute, the CPU may fetch further data from RAM by placing an address on the address bus and reading the value back on the data bus → MAR ← 50, MDR ← RAM[MAR]
During execute, the result of an ALU calculation is stored in the accumulator → ACC ← ALU result
Execute stage: the instruction is copied from the PC into the MAR → This describes the start of the fetch stage, not execute. In execute the decoded instruction is carried out, e.g. an ALU calculation or a change to the PC.
Execute: the ALU calculates and the result is stored in the MAR → The result of an ALU calculation is stored in the accumulator (ACC), not the MAR. The MAR only holds a memory address.

Key Term

execute
The stage of the fetch-decode-execute cycle where the decoded instruction is carried out, e.g. fetching data, calculating in the ALU, storing in the ACC, or changing the PC.

Fill in the Blanks

1. Execute ADD: ACC ← ACC + MDR
Hint: Type the register that holds the data just fetched from RAM
2. The result of the ALU is stored in the ACC
Hint: Type the register that holds the result of calculations
3. Execute JMP 20: PC ← 20
Hint: Type the register that a jump instruction changes
4. LDA 50: address 50 sent on the address bus
Hint: Type the name of the bus that carries a memory location
5. Execute: ALU adds, ACC stores the result
Hint: Type the CPU component that carries out calculations

Spot the Error

Question 1
A IF opcode = JMP THEN
B ALU adds operand to ACC
C ACC <- result
D ENDIF
Line A — The ALU adds the operand to the ACC only when the decoded opcode is ADD. A JMP instruction changes the PC instead. The line should be IF opcode = ADD THEN.
Question 2
A LDA 40 executes:
B PC <- 40
C MDR <- RAM[MAR]
D ACC <- MDR
Line B — LDA loads data from address 40, so the address goes into the MAR to read RAM. Putting it in the PC would make the CPU jump instead. It should be MAR <- 40.
Question 3
A ADD 40 executes:
B MAR <- 40
C MDR <- RAM[MAR]
D ACC <- ACC - MDR
Line D — ADD makes the ALU add the fetched data to the ACC. The line subtracts instead. It should be ACC <- ACC + MDR.
Question 4
A JMP 90 executes:
B ACC <- 90
C Next fetch uses address 90
Line B — A jump changes the PC so the next fetch reads from the new address. It does not store a value in the ACC. It should be PC <- 90.
Question 5
A STA 50 executes:
B MDR <- 50
C MDR <- ACC
D RAM[MAR] <- MDR
Line B — The address 50 tells the CPU where to store the ACC value, so it goes into the MAR. The MDR holds the data being written. It should be MAR <- 50.

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