← IGCSE Computer Science Paper 1

Tracing one instruction through the registers

Recording the contents of the PC, MAR, MDR, CIR and ACC, and the bus used, at each step as one instruction goes through the fetch-decode-execute cycle.

Part of: IGCSE Computer Science 0478 — 3.1 Computer Architecture — Module 24

Understanding Tracing one instruction through the registers in IGCSE Computer Science Paper 1

What it does: Checking the PC after each fetch in a trace table shows it has gone up by 1, ready for the next instruction. The PC holds an address, not an instruction. Step 1 of the trace is MAR = 100. The address bus carries memory addresses one way, from the CPU to RAM. The data bus carries the contents. The data bus carries data and instructions between RAM and the CPU. The MDR then holds ADD 5. Signals such as read and write travel on the control bus. They are not data or addresses. The instruction is copied from the MDR to the CIR, where it is decoded. The PC does not go into the CIR.

Common mistakes: The instruction travels from RAM to the MDR on the data bus. The address bus only carries the address from the MAR to RAM. The line should say (data bus). The PC is incremented during every fetch, so after the fetch it must hold 101, not 100. It should read PC = 101 after fetch.

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Learning
Duo
A trace starts with the PC holding 100. What is copied to the MAR in the first step of the fetch?
The address 100, copied from the PCThe instruction stored at address 100
Matches
PC: 100 → 100 (after fetch)
↓
The PC has not been incremented. After the fetch the PC should be 101, so it points to the next instruction.
Applying
Meanings
Term
register trace
Meaning
Recording the contents of the PC, MAR, MDR, CIR and ACC, and the bus used, at each step as one instruction goes through the fetch-decode-execute cycle.
Practice
PC = 100
Testing
Gaps
MAR ←
Check Answer
Spots
2MAR <- PC (address bus)
3MDR <- RAM[100] (address bus)

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Quick Questions

1. A trace starts with the PC holding 100. What is copied to the MAR in the first step of the fetch?
A. The address 100, copied from the PC ✓
B. The instruction stored at address 100
The PC holds an address, not an instruction. Step 1 of the trace is MAR = 100.
2. In the trace, the address 100 travels from the MAR to RAM. Which bus is used?
A. Data bus
B. Address bus ✓
The address bus carries memory addresses one way, from the CPU to RAM. The data bus carries the contents.
3. RAM at address 100 holds ADD 5. Which bus carries 'ADD 5' back to the MDR?
A. Data bus ✓
B. Address bus
The data bus carries data and instructions between RAM and the CPU. The MDR then holds ADD 5.
4. The PC held 100 at the start of the fetch. What should the trace table show in the PC once the fetch has finished?
A. 101 ✓
B. 100
The PC is incremented during the fetch so it points to the next instruction. 100 becomes 101.
5. During the fetch, the control unit sends a 'read' signal to RAM. Which bus carries it?
A. Data bus
B. Control bus ✓
Signals such as read and write travel on the control bus. They are not data or addresses.

Match the Pairs

PC: 100 → MAR: 100 → The address of the next instruction is copied from the PC to the MAR at the start of the fetch stage, using the address bus.
MDR: LDA 50 → CIR: LDA 50 → The instruction fetched from RAM is copied from the MDR to the CIR so it can be decoded, and the PC has already been incremented.
After each fetch, the PC is incremented by 1 so it points to the next instruction in the program. → PC: 100 → 101
When the MAR sends an address to RAM, the control bus carries a read signal and the data bus returns the contents of that address. → MAR: 100 | Bus: address | MDR: ADD 7
PC: 100 → 100 (after fetch) → The PC has not been incremented. After the fetch the PC should be 101, so it points to the next instruction.
MAR: 100 | Bus used: data bus → The MAR sends an address, so the bus used is the address bus. The data bus carries the contents of the memory location.

Key Term

register trace
Recording the contents of the PC, MAR, MDR, CIR and ACC, and the bus used, at each step as one instruction goes through the fetch-decode-execute cycle.

Fill in the Blanks

1. PC = 100 MAR ← PC Bus used: address bus
Hint: Type the register whose value is copied into the MAR at the start of the fetch.
2. MAR = 100 MDR ← RAM[MAR] Bus used: data bus
Hint: Type the kind of bus that carries the instruction from RAM to the MDR.
3. Before fetch: PC = 100 MAR ← PC, PC ← PC + 1 After fetch: PC = 101
Hint: Type the number the PC holds once it has been incremented by one.
4. MDR = LDA 200 CIR ← MDR Decode: CU reads the CIR
Hint: Type the register whose contents are copied into the CIR.
5. CIR = LDA 200 Execute: ACC ← RAM[200] Bus used: data bus
Hint: Type the register that stores the value loaded from RAM by this instruction.

Spot the Error

Question 1
A PC = 100
B MAR <- PC (address bus)
C MDR <- RAM[100] (address bus)
D CIR <- MDR
E PC <- PC + 1
Line C — The instruction travels from RAM to the MDR on the data bus. The address bus only carries the address from the MAR to RAM. The line should say (data bus).
Question 2
A PC = 100 before fetch
B MAR = 100
C MDR = LOAD 200
D PC = 100 after fetch
Line D — The PC is incremented during every fetch, so after the fetch it must hold 101, not 100. It should read PC = 101 after fetch.
Question 3
A PC = 100
B MAR <- ACC
C MDR <- RAM[MAR]
D CIR <- MDR
Line B — The first step of a fetch copies the address in the PC into the MAR. The ACC holds data values, not instruction addresses. The line should be MAR <- PC.
Question 4
A Decode: CIR = ADD 5
B Execute: ACC <- ACC - 5
C ACC was 3, so ACC = 8
Line B — The instruction in the CIR is ADD 5, so the ALU adds 5 to the ACC. It does not subtract. The line should be ACC <- ACC + 5, which gives 8.
Question 5
A PC = 150
B MAR = 100
C MDR = ADD 5
D CIR = ADD 5
Line A — The MAR is a copy of the PC at the start of the fetch. MAR is 100, so the PC must also be 100. The line should be PC = 100.

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