Tracing one instruction through the registers

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Tracing one instruction through the registers

Name:
Date:
Class:
A

Quick Questions

Shade in the A or B circle for each question.

1. A trace starts with the PC holding 100. What is copied to the MAR in the first step of the fetch?
A The address 100, copied from the PC
B The instruction stored at address 100
2. In the trace, the address 100 travels from the MAR to RAM. Which bus is used?
A Data bus
B Address bus
3. RAM at address 100 holds ADD 5. Which bus carries 'ADD 5' back to the MDR?
A Data bus
B Address bus
4. The PC held 100 at the start of the fetch. What should the trace table show in the PC once the fetch has finished?
A 101
B 100
5. During the fetch, the control unit sends a 'read' signal to RAM. Which bus carries it?
A Data bus
B Control bus
B

Match the Pairs

Draw a line connecting each item on the left to its match on the right.

Left columnRight column
1PC: 100 → MAR: 100 AMAR: 100 | Bus: address | MDR: ADD 7
2MDR: LDA 50 → CIR: LDA 50 BThe address of the next instruction is copied from the PC to the MAR at the start of the fetch stage, using the address bus.
3After each fetch, the PC is incremented by 1 so it points to the next instruction in the program. CThe PC has not been incremented. After the fetch the PC should be 101, so it points to the next instruction.
4When the MAR sends an address to RAM, the control bus carries a read signal and the data bus returns the contents of that address. DThe instruction fetched from RAM is copied from the MDR to the CIR so it can be decoded, and the PC has already been incremented.
5PC: 100 → 100 (after fetch) EThe MAR sends an address, so the bus used is the address bus. The data bus carries the contents of the memory location.
6MAR: 100 | Bus used: data bus FPC: 100 → 101
C

Definitions

register trace
D

Fill in the Blanks

Complete each line of code by filling in the missing parts.

1.
PC = 100 MAR ← __ Bus used: address bus
2.
MAR = 100 MDR ← RAM[MAR] Bus used: ____ bus
3.
Before fetch: PC = 100 MAR ← PC, PC ← PC + 1 After fetch: PC = ___
4.
MDR = LDA 200 CIR ← ___ Decode: CU reads the CIR
5.
CIR = LDA 200 Execute: ___ ← RAM[200] Bus used: data bus
E

Spot the Error

Shade in the letter of the line that contains an error.

Question 1
A PC = 100
B MAR <- PC (address bus)
C MDR <- RAM[100] (address bus)
D CIR <- MDR
E PC <- PC + 1
Question 2
A PC = 100 before fetch
B MAR = 100
C MDR = LOAD 200
D PC = 100 after fetch
Question 3
A PC = 100
B MAR <- ACC
C MDR <- RAM[MAR]
D CIR <- MDR
Question 4
A Decode: CIR = ADD 5
B Execute: ACC <- ACC - 5
C ACC was 3, so ACC = 8
Question 5
A PC = 150
B MAR = 100
C MDR = ADD 5
D CIR = ADD 5

Answer Key

Tracing one instruction through the registers
Section A: Quick Questions
Q1
A — The address 100, copied from the PC
Q2
B — Address bus
Q3
A — Data bus
Q4
A — 101
Q5
B — Control bus
Section B: Match the Pairs
Q1
PC: 100 → MAR: 100 → The address of the next instruction is copied from the PC to the MAR at the start of the fetch stage, using the address bus.
Q2
MDR: LDA 50 → CIR: LDA 50 → The instruction fetched from RAM is copied from the MDR to the CIR so it can be decoded, and the PC has already been incremented.
Q3
After each fetch, the PC is incremented by 1 so it points to the next instruction in the program. → PC: 100 → 101
Q4
When the MAR sends an address to RAM, the control bus carries a read signal and the data bus returns the contents of that address. → MAR: 100 | Bus: address | MDR: ADD 7
Q5
PC: 100 → 100 (after fetch) → The PC has not been incremented. After the fetch the PC should be 101, so it points to the next instruction.
Q6
MAR: 100 | Bus used: data bus → The MAR sends an address, so the bus used is the address bus. The data bus carries the contents of the memory location.
Section C: Definitions
Q1
register trace — Recording the contents of the PC, MAR, MDR, CIR and ACC, and the bus used, at each step as one instruction goes through the fetch-decode-execute cycle.
Section D: Fill in the Blanks
Q1
PC = 100 MAR ← PC Bus used: address bus
Q2
MAR = 100 MDR ← RAM[MAR] Bus used: data bus
Q3
Before fetch: PC = 100 MAR ← PC, PC ← PC + 1 After fetch: PC = 101
Q4
MDR = LDA 200 CIR ← MDR Decode: CU reads the CIR
Q5
CIR = LDA 200 Execute: ACC ← RAM[200] Bus used: data bus
Section E: Spot the Error
Q1
C — The instruction travels from RAM to the MDR on the data bus. The address bus only carries the address from the MAR to RAM. The line should say (data bus).
Q2
D — The PC is incremented during every fetch, so after the fetch it must hold 101, not 100. It should read PC = 101 after fetch.
Q3
B — The first step of a fetch copies the address in the PC into the MAR. The ACC holds data values, not instruction addresses. The line should be MAR <- PC.
Q4
B — The instruction in the CIR is ADD 5, so the ALU adds 5 to the ACC. It does not subtract. The line should be ACC <- ACC + 5, which gives 8.
Q5
A — The MAR is a copy of the PC at the start of the fetch. MAR is 100, so the PC must also be 100. The line should be PC = 100.