← IGCSE Computer Science Paper 1

Fetch: reading the instruction from RAM into the MDR

Fetch step: RAM finds the instruction at the address in the MAR (address bus), a read signal comes via the control bus, and the instruction travels on the data bus into the MDR.

Part of: IGCSE Computer Science 0478 — 3.1 Computer Architecture — Module 20

Understanding Fetch: reading the instruction from RAM into the MDR in IGCSE Computer Science Paper 1

What it does: The address travels one way, from the MAR to RAM, on the address bus. It tells RAM which location to look at. After RAM finds the instruction, it sends it along the data bus, and the MDR stores it temporarily before it is copied to the CIR. The MAR only holds the address. The instruction that is read from RAM is copied into the MDR (MDR <- RAM[MAR]). The address bus is one-way. The CPU sends the address to RAM, and RAM never sends addresses back on it. RAM[MAR] means the RAM location whose address is in the MAR, and the arrow shows its contents being stored in the MDR during the fetch stage.

Common mistakes: The instruction travels along the data bus from RAM into the MDR, not the MAR. The MAR only holds the address. It should be Data bus: RAM -> MDR. The address bus carries the address from the MAR to RAM, not the other way round. It should be Address bus: MAR -> RAM.

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This module's key terms are also in a printable crossword (Modules 228–239) and word search (Modules 218–239).

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Learning
Duo
During the fetch stage, where does the instruction at the address held in the MAR get stored after it is read from RAM?
In the MARIn the MDR
Matches
RAM --address bus--> MDR
↓
The address bus carries addresses from the MAR to RAM, not the instruction from RAM to the MDR. The instruction travels on the data bus.
Applying
Meanings
Term
MDR <- RAM[MAR]
Meaning
Fetch step: RAM finds the instruction at the address in the MAR (address bus), a read signal comes via the control bus, and the instruction travels on the data bus into the MDR.
Practice
MAR <- PC
Testing
Gaps
← RAM[MAR]
Check Answer
Spots
3Control bus: read signal
4Data bus: RAM -> MAR

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Quick Questions

1. During the fetch stage, where does the instruction at the address held in the MAR get stored after it is read from RAM?
A. In the MDR ✓
B. In the MAR
The MAR only holds the address. The instruction that is read from RAM is copied into the MDR (MDR <- RAM[MAR]).
2. Which bus carries the address from the MAR to RAM so RAM can find the instruction?
A. Address bus ✓
B. Data bus
The address bus carries the address of the memory location. It is one-way, from the CPU to RAM.
3. Which bus carries the read signal that tells RAM to send back the contents of the memory location?
A. Address bus
B. Control bus ✓
The control bus carries control signals such as read and write. The address bus only carries addresses.
4. Which bus carries the instruction from RAM back to the CPU?
A. Data bus ✓
B. Control bus
The data bus carries data and instructions between RAM and the CPU. The instruction travels along it into the MDR.
5. Which statement describes the fetch step MDR <- RAM[MAR] correctly?
A. The contents of the MAR are copied into the MDR without using RAM
B. The contents of the RAM location whose address is in the MAR are copied into the MDR ✓
RAM[MAR] means the value stored in RAM at the address held in the MAR. That value is copied into the MDR.

Match the Pairs

MDR <- RAM[MAR] → The instruction stored in RAM at the address held in the MAR is copied into the MDR
Control bus: READ signal sent to RAM → Tells RAM to read the instruction at the requested address and send it back to the CPU
The address bus carries the address from the MAR to RAM so RAM can find the instruction → MAR --address bus--> RAM
The data bus carries the instruction from RAM back to the MDR → RAM --data bus--> MDR
RAM --address bus--> MDR → The address bus carries addresses from the MAR to RAM, not the instruction from RAM to the MDR. The instruction travels on the data bus.
MAR <- RAM[MDR] → RAM is looked up using the address in the MAR, not the MDR. The instruction is then stored in the MDR, so the registers are the wrong way round.

Key Term

MDR <- RAM[MAR]
Fetch step: RAM finds the instruction at the address in the MAR (address bus), a read signal comes via the control bus, and the instruction travels on the data bus into the MDR.

Fill in the Blanks

1. MDR ← RAM[MAR]
Hint: Type the register that receives the instruction copied from RAM.
2. MDR ← RAM[MAR]
Hint: Type the register that holds the address of the instruction to read.
3. The address bus sends the MAR value to RAM
Hint: Type the bus that carries the memory location to RAM.
4. The control bus carries the read signal
Hint: Type the bus that carries signals such as read.
5. The data bus carries the instruction to the MDR
Hint: Type the bus that carries the instruction itself back from RAM.

Spot the Error

Question 1
A MAR <- PC
B Address bus: MAR -> RAM
C Control bus: read signal
D Data bus: RAM -> MAR
Line D — The instruction travels along the data bus from RAM into the MDR, not the MAR. The MAR only holds the address. It should be Data bus: RAM -> MDR.
Question 2
A MAR <- 100
B Address bus: RAM -> MAR
C Control bus: read signal
Line B — The address bus carries the address from the MAR to RAM, not the other way round. It should be Address bus: MAR -> RAM.
Question 3
A MAR <- PC
B Control bus: write signal
C Data bus: RAM -> MDR
Line B — To fetch an instruction, RAM is told to read. The control bus carries a read signal, not a write signal. It should be Control bus: read signal.
Question 4
A MAR <- PC
B Address bus: MAR -> RAM
C MDR <- RAM[PC]
D CIR <- MDR
Line C — RAM is read at the address held in the MAR, because the address was sent along the address bus from the MAR. It should be MDR <- RAM[MAR].
Question 5
A RAM reads address in MDR
B Data bus: RAM -> MDR
C MDR holds the instruction
Line A — The address of the instruction is held in the MAR. The MDR holds the data or instruction that comes back. It should be RAM reads address in MAR.

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