Fetch: reading the instruction from RAM into the MDR

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Quick Questions

Shade in the A or B circle for each question.

1. During the fetch stage, where does the instruction at the address held in the MAR get stored after it is read from RAM?

A In the MDR

B In the MAR

2. Which bus carries the address from the MAR to RAM so RAM can find the instruction?

A Address bus

B Data bus

3. Which bus carries the read signal that tells RAM to send back the contents of the memory location?

A Address bus

B Control bus

4. Which bus carries the instruction from RAM back to the CPU?

A Data bus

B Control bus

5. Which statement describes the fetch step MDR <- RAM[MAR] correctly?

A The contents of the MAR are copied into the MDR without using RAM

B The contents of the RAM location whose address is in the MAR are copied into the MDR

Match the Pairs

Draw a line connecting each item on the left to its match on the right.

Left column		Right column
1MDR <- RAM[MAR]		ARAM --data bus--> MDR
2Control bus: READ signal sent to RAM		BRAM is looked up using the address in the MAR, not the MDR. The instruction is then stored in the MDR, so the registers are the wrong way round.
3The address bus carries the address from the MAR to RAM so RAM can find the instruction		CThe address bus carries addresses from the MAR to RAM, not the instruction from RAM to the MDR. The instruction travels on the data bus.
4The data bus carries the instruction from RAM back to the MDR		DMAR --address bus--> RAM
5RAM --address bus--> MDR		EThe instruction stored in RAM at the address held in the MAR is copied into the MDR
6MAR <- RAM[MDR]		FTells RAM to read the instruction at the requested address and send it back to the CPU

Definitions

MDR <- RAM[MAR]

Fill in the Blanks

Complete each line of code by filling in the missing parts.

___ ← RAM[MAR]

MDR ← RAM[___]

The _______ bus sends the MAR value to RAM

The _______ bus carries the read signal

The ____ bus carries the instruction to the MDR

Spot the Error

Shade in the letter of the line that contains an error.

Question 1

A MAR <- PC

B Address bus: MAR -> RAM

C Control bus: read signal

D Data bus: RAM -> MAR

Question 2

A MAR <- 100

B Address bus: RAM -> MAR

C Control bus: read signal

Question 3

A MAR <- PC

B Control bus: write signal

C Data bus: RAM -> MDR

Question 4

A MAR <- PC

B Address bus: MAR -> RAM

C MDR <- RAM[PC]

D CIR <- MDR

Question 5

A RAM reads address in MDR

B Data bus: RAM -> MDR

C MDR holds the instruction

Answer Key

Fetch: reading the instruction from RAM into the MDR

Section A: Quick Questions

A — In the MDR

A — Address bus

B — Control bus

A — Data bus

B — The contents of the RAM location whose address is in the MAR are copied into the MDR

Section B: Match the Pairs

MDR <- RAM[MAR] → The instruction stored in RAM at the address held in the MAR is copied into the MDR

Control bus: READ signal sent to RAM → Tells RAM to read the instruction at the requested address and send it back to the CPU

The address bus carries the address from the MAR to RAM so RAM can find the instruction → MAR --address bus--> RAM

The data bus carries the instruction from RAM back to the MDR → RAM --data bus--> MDR

RAM --address bus--> MDR → The address bus carries addresses from the MAR to RAM, not the instruction from RAM to the MDR. The instruction travels on the data bus.

MAR <- RAM[MDR] → RAM is looked up using the address in the MAR, not the MDR. The instruction is then stored in the MDR, so the registers are the wrong way round.

Section C: Definitions

MDR <- RAM[MAR] — Fetch step: RAM finds the instruction at the address in the MAR (address bus), a read signal comes via the control bus, and the instruction travels on the data bus into the MDR.

Section D: Fill in the Blanks

MDR ← RAM[MAR]

The address bus sends the MAR value to RAM

The control bus carries the read signal

The data
 bus carries the instruction to the MDR

Section E: Spot the Error

D — The instruction travels along the data bus from RAM into the MDR, not the MAR. The MAR only holds the address. It should be Data bus: RAM -> MDR.

B — The address bus carries the address from the MAR to RAM, not the other way round. It should be Address bus: MAR -> RAM.

B — To fetch an instruction, RAM is told to read. The control bus carries a read signal, not a write signal. It should be Control bus: read signal.

C — RAM is read at the address held in the MAR, because the address was sent along the address bus from the MAR. It should be MDR <- RAM[MAR].

A — The address of the instruction is held in the MAR. The MDR holds the data or instruction that comes back. It should be RAM reads address in MAR.