← IGCSE Computer Science Paper 1

Writing exam answers about the CPU

A full-mark CPU answer uses exact names for registers, buses and units, and gives the fetch, decode and execute steps in order, e.g. PC to MAR, then MDR, then CIR.

Part of: IGCSE Computer Science 0478 — 3.1 Computer Architecture — Module 35

Understanding Writing exam answers about the CPU in IGCSE Computer Science Paper 1

What it does: The cycle always runs fetch, then decode, then execute, so an exam answer must keep this order. The MAR uses the address bus to send a location, and the MDR uses the data bus to carry contents, so the two must not be mixed up. The PC holds the address of the next instruction and it is copied to the MAR. The MDR holds data or instructions that have been read from or are about to be written to RAM. An instruction must be fetched from RAM before the control unit can decode it, and it must be decoded before it can be executed.

Common mistakes: The instruction arrives in the MDR, so the MDR copies it to the CIR. The MAR only holds an address, never the instruction. The address from the PC is copied to the MAR, not the MDR. The MDR holds the data that comes back from RAM.

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This module's key terms are also in a printable crossword (Modules 240–251) and word search (Modules 240–261).

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Learning
Duo
Which sentence would earn the mark for the first step of the fetch stage?
The address in the PC is copied to the MAR.The address in the PC is copied to the MDR.
Matches
The MDR holds the address of the next instruction.
↓
Mixing up the MAR and MDR: the MAR holds the address, the MDR holds the data or instruction fetched from that address.
Applying
Meanings
Term
fetch-decode-execute
Meaning
A full-mark CPU answer uses exact names for registers, buses and units, and gives the fetch, decode and execute steps in order, e.g. PC to MAR, then MDR, then CIR.
Practice
Fetch: the PC sends the address to the MAR.
Testing
Gaps
MAR ←
Check Answer
Spots
22 Instruction read into MDR
33 MAR copies it to the CIR

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Quick Questions

1. Which sentence would earn the mark for the first step of the fetch stage?
A. The address in the PC is copied to the MAR. ✓
B. The address in the PC is copied to the MDR.
The PC holds the address of the next instruction and it is copied to the MAR. The MDR holds data or instructions that have been read from or are about to be written to RAM.
2. Which answer uses the correct term for the bus that carries the location in RAM to be read?
A. The address bus carries the memory address from the MAR to RAM. ✓
B. The data bus carries the memory address from the MAR to RAM.
Addresses travel on the address bus, which is one-way from the CPU to memory. The data bus carries the actual data or instructions.
3. Which describes the correct order of the FDE cycle in an exam answer?
A. Decode, then fetch, then execute.
B. Fetch, then decode, then execute. ✓
An instruction must be fetched from RAM before the control unit can decode it, and it must be decoded before it can be executed.
4. Which statement is correct about the MDR in the fetch stage?
A. The instruction read from RAM is placed in the MDR. ✓
B. The instruction read from RAM is placed in the MAR.
The MAR only stores the address. The MDR holds the instruction or data that is fetched, which is then copied to the CIR.
5. Which answer gives a full-mark reason for why more cores can improve performance?
A. More cores make the computer faster because it has more cores.
B. More cores can process more instructions at the same time, so more work is done. ✓
A full-mark answer gives a reason. Each core can run its own instructions, so tasks can be shared between cores. Repeating the question does not earn marks.

Match the Pairs

PC → MAR → The address of the next instruction is copied from the program counter to the memory address register at the start of fetch.
RAM → MDR → CIR → The instruction is read from memory into the memory data register, then copied to the current instruction register.
The correct order of the stages in the cycle must be given in a full-mark answer. → fetch, decode, execute
The address bus carries the memory location from the MAR, while the data bus carries the instruction or data itself. → MAR → address bus, MDR ↔ data bus
The MDR holds the address of the next instruction. → Mixing up the MAR and MDR: the MAR holds the address, the MDR holds the data or instruction fetched from that address.
A faster clock speed means the CPU has more memory. → Clock speed is the number of cycles per second, not the amount of memory. A higher speed lets more instructions run each second, so performance rises.

Key Term

fetch-decode-execute
A full-mark CPU answer uses exact names for registers, buses and units, and gives the fetch, decode and execute steps in order, e.g. PC to MAR, then MDR, then CIR.

Fill in the Blanks

1. MAR ← PC
Hint: Type the register that holds the address of the next instruction and is copied into the MAR first.
2. MDR ← RAM[MAR]
Hint: Type the register whose stored address tells RAM which location to read.
3. CIR ← MDR
Hint: Type the register that temporarily holds the instruction just read from RAM before it is copied to the CIR.
4. The MAR sends the address on the address bus
Hint: Type the word that names the bus carrying a memory location, not the data.
5. Fetch, decode, execute
Hint: Type the name of the middle stage of the cycle, where the CU works out what the instruction means.

Spot the Error

Question 1
A 1 PC sends address to MAR
B 2 Instruction read into MDR
C 3 MAR copies it to the CIR
D 4 PC is incremented by one
Line C — The instruction arrives in the MDR, so the MDR copies it to the CIR. The MAR only holds an address, never the instruction.
Question 2
A Fetch: address goes PC to MDR
B Fetch: data comes back to MDR
C Decode: CU decodes the CIR
D Execute: ALU or CU acts
Line A — The address from the PC is copied to the MAR, not the MDR. The MDR holds the data that comes back from RAM.
Question 3
A Address bus carries the data
B Data bus carries instructions
C Control bus carries signals
Line A — The address bus carries memory addresses only. The data bus carries the data and instructions.
Question 4
A The ALU does the calculations
B The ALU decodes instructions
C The ACC stores ALU results
Line B — The control unit (CU) decodes instructions. The ALU does arithmetic and logic.
Question 5
A A higher clock speed means
B more cycles each second,
C so more instructions run
D per second, so CPU is slower
Line D — More cycles per second means more instructions are processed each second, so the CPU is faster, not slower.

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