Memory data register (MDR)

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Quick Questions

Shade in the A or B circle for each question.

1. What does the MDR hold?

A The data or instruction just fetched from RAM, or data about to be written to RAM

B The address of the next instruction to be fetched

2. Which register holds a memory ADDRESS, not data?

A MAR

B MDR

3. How does the MDR act between the CPU and RAM?

A As a buffer: data waits in the MDR as it travels between them

B As a store for the memory addresses used by the CPU

4. During the fetch stage, where is the instruction placed first after it is read from RAM?

A Straight into the CIR

B In the MDR

5. The MDR is used when data is being written to RAM as well as when it is being read from RAM.

A False

B True

Match the Pairs

Draw a line connecting each item on the left to its match on the right.

Left column		Right column
1MDR		AThe MDR cannot supply the address to RAM. The address must come from the MAR, and the fetched contents are then placed into the MDR.
2MDR <- RAM[MAR]		BThe MDR holds data or instructions, not addresses. Addresses are held in the MAR (and the PC holds the address of the next instruction).
3The MDR is a buffer between the CPU and RAM: everything travelling between them passes through it first		CMemory Data Register: a CPU register that temporarily holds the data or instruction just fetched from RAM, or data about to be written to RAM
4After a fetch, the instruction waits in the MDR and is then moved to the CIR to be decoded		DThe instruction or data stored at the address held in the MAR is copied from RAM into the MDR during the fetch stage
5MDR holds the address of the next instruction		ERAM -> MDR -> CPU
6MAR <- RAM[MDR]		FCIR <- MDR

Definitions

MDR

Fill in the Blanks

Complete each line of code by filling in the missing parts.

___ ← RAM[MAR]

CIR ← ___

MAR ← PC MDR ← RAM[___] CIR ← MDR

RAM[MAR] ← ___

// The MDR holds ____, not addresses

Spot the Error

Shade in the letter of the line that contains an error.

Question 1

A MDR ← PC

B MDR ← RAM[MAR]

C CIR ← MDR

Question 2

A MAR ← PC

B MDR ← RAM[MAR]

C CIR ← MAR

D PC ← PC + 1

Question 3

A MAR ← 120

B MDR ← RAM[MAR]

C ACC ← MAR

Question 4

A MAR ← PC

B MDR ← RAM[MAR]

C PC ← PC + 1

D MDR ← CIR

Question 5

A MAR ← 150

B ACC ← MDR

C RAM[MAR] ← MDR

Answer Key

Memory data register (MDR)

Section A: Quick Questions

A — The data or instruction just fetched from RAM, or data about to be written to RAM

A — MAR

A — As a buffer: data waits in the MDR as it travels between them

B — In the MDR

B — True

Section B: Match the Pairs

MDR → Memory Data Register: a CPU register that temporarily holds the data or instruction just fetched from RAM, or data about to be written to RAM

MDR <- RAM[MAR] → The instruction or data stored at the address held in the MAR is copied from RAM into the MDR during the fetch stage

The MDR is a buffer between the CPU and RAM: everything travelling between them passes through it first → RAM -> MDR -> CPU

After a fetch, the instruction waits in the MDR and is then moved to the CIR to be decoded → CIR <- MDR

MDR holds the address of the next instruction → The MDR holds data or instructions, not addresses. Addresses are held in the MAR (and the PC holds the address of the next instruction).

MAR <- RAM[MDR] → The MDR cannot supply the address to RAM. The address must come from the MAR, and the fetched contents are then placed into the MDR.

Section C: Definitions

MDR — Memory Data Register: a CPU register that temporarily holds the data or instruction just fetched from RAM, or data about to be written to RAM. It holds data, not addresses.

Section D: Fill in the Blanks

MDR ← RAM[MAR]

CIR ← MDR

MAR ← PC
MDR ← RAM[MAR]
CIR ← MDR

RAM[MAR] ← MDR

// The MDR holds data, not addresses

Section E: Spot the Error

A — The PC holds an address, and the MDR holds data, not addresses. The address from the PC must go into the MAR: MAR ← PC.

C — The fetched instruction waits in the MDR before it moves to the CIR. The MAR only holds an address. It should be CIR ← MDR.

C — The data fetched from RAM is held in the MDR, so the ACC must receive it from the MDR. The MAR holds an address, not data. It should be ACC ← MDR.

D — The data flows the wrong way. In the fetch stage the instruction is copied from the MDR into the CIR, so it should be CIR ← MDR.

B — Data about to be written to RAM is placed in the MDR first. The value must go from the ACC into the MDR, so it should be MDR ← ACC.