Decode stage

Name:

Date:

Class:

Quick Questions

Shade in the A or B circle for each question.

1. Which part of the CPU carries out the decode stage?

A The control unit (CU)

B The arithmetic logic unit (ALU)

2. Where is the instruction held while it is being decoded?

A The program counter (PC)

B The current instruction register (CIR)

3. Which statement describes the decode stage correctly?

A The CU works out what the instruction means and what data it needs

B The CU adds 1 to the PC and fetches the next instruction

4. An instruction is made of two parts. What are they?

A An operation and an operand

B An address bus and a data bus

5. In the instruction ADD 5, which part is the operand?

A ADD

B 5

Match the Pairs

Draw a line connecting each item on the left to its match on the right.

Left column		Right column
1LDA 25		AADD 7 (operation = ADD)
2CIR → CU		BThe decode stage: the control unit reads the instruction held in the current instruction register
3The operation part of an instruction tells the CU what action to carry out		CCU looks up opcode in instruction set
4The CU uses the instruction set to understand what a command in the CIR means		DThe control unit decodes the instruction, not the ALU. The ALU only does arithmetic and logic during execute.
5Decode: the ALU reads the CIR and works out the instruction		EAn instruction made of an operation (LDA, load) and an operand (25) that the control unit works out during decode
6Decode: the instruction is fetched from RAM into the MDR		FThis describes the fetch stage. Decode happens after fetch, when the CU works out the operation and operand from the CIR.

Definitions

Decode

Fill in the Blanks

Complete each line of code by filling in the missing parts.

The __ decodes the instruction in the CIR

LDA 20 : operation = LDA, _______ = 20

CU reads the ___ to decode the instruction

The CU uses the _______________ to decode

Instruction: ADD 7 Operation: ___ Operand: 7

Spot the Error

Shade in the letter of the line that contains an error.

Question 1

A CIR <- 'ADD 5'

B operation <- '5'

C operand <- 5

D CU decodes the CIR

Question 2

A Fetch puts instruction in CIR

B Decode begins

C CU reads the CIR

D CU checks the cache size

Question 3

A instruction <- CIR

B operation <- 'LOAD'

C operand <- 20

D RAM looks up the operation

Question 4

A CU reads instruction from PC

B operation <- 'STORE'

C operand <- 50

Question 5

A CIR <- 'LOAD 40'

B operand <- 'LOAD'

C operation <- 'LOAD'

Answer Key

Decode stage

Section A: Quick Questions

A — The control unit (CU)

B — The current instruction register (CIR)

A — The CU works out what the instruction means and what data it needs

A — An operation and an operand

B — 5

Section B: Match the Pairs

LDA 25 → An instruction made of an operation (LDA, load) and an operand (25) that the control unit works out during decode

CIR → CU → The decode stage: the control unit reads the instruction held in the current instruction register

The operation part of an instruction tells the CU what action to carry out → ADD 7 (operation = ADD)

The CU uses the instruction set to understand what a command in the CIR means → CU looks up opcode in instruction set

Decode: the ALU reads the CIR and works out the instruction → The control unit decodes the instruction, not the ALU. The ALU only does arithmetic and logic during execute.

Decode: the instruction is fetched from RAM into the MDR → This describes the fetch stage. Decode happens after fetch, when the CU works out the operation and operand from the CIR.

Section C: Definitions

Decode — The fetch-decode-execute stage where the control unit reads the instruction in the CIR and works out the operation to perform and the data (operand) it needs.

Section D: Fill in the Blanks

The CU decodes the instruction in the CIR

LDA 20 : operation = LDA, operand = 20

CU reads the CIR to decode the instruction

The CU uses the instruction set to decode

Instruction: ADD 7
Operation: ADD
Operand: 7

Section E: Spot the Error

B — The operation is the command to perform, here ADD. The 5 is the operand (the data). It should be operation <- 'ADD'.

D — The CU uses the instruction set to understand what the command means. Cache size does not help it decode. It should be 'CU checks the instruction set'.

D — The control unit, not RAM, looks up the operation to work out what it means. It should be 'CU looks up the operation'.

A — The instruction to decode is held in the CIR. The PC only holds the address of the next instruction. It should be 'from CIR'.

B — LOAD is the operation. The operand is the data or address the instruction needs, here 40. It should be operand <- 40 on that line's role, so operand <- 40.