Data bus

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Data bus

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Date:
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Quick Questions

Shade in the A or B circle for each question.

1. The data bus carries data and instructions between the CPU and RAM.
A True
B False
2. Which direction can the data bus carry signals?
A Both directions (two-way)
B One direction only (CPU to RAM)
3. Which register does the data bus connect to in the CPU?
A Memory address register (MAR)
B Memory data register (MDR)
4. The data bus carries only data and never instructions.
A False
B True
5. Which bus carries the instruction from RAM to the CPU during the fetch stage?
A Address bus
B Data bus

Match the Pairs

Draw a line connecting each item on the left to its match on the right.

Left columnRight column
1data bus ARAM --data bus--> MDR (instruction)
2MDR <-> Data bus <-> RAM BThe data bus carries instructions as well as data. Instructions are fetched from RAM along it into the MDR.
3The data bus carries instructions as well as data, so a fetched instruction travels along it from RAM to the CPU CThe data bus works in both directions: the MDR can send data to RAM or receive data from RAM
4The data bus is two-way, so the CPU can both read from RAM and write to RAM DA set of wires that carries data and instructions between the CPU and RAM
5The data bus carries only data, never instructions EThe data bus is two-way (bidirectional). It carries values from RAM to the CPU and from the CPU to RAM. Only the address bus is one-way.
6The data bus is one-way: CPU -> RAM only FRead: RAM -> MDR | Write: MDR -> RAM

Definitions

data bus

Fill in the Blanks

Complete each line of code by filling in the missing parts.

1.
The data ___ links the CPU and RAM
2.
Data bus: _______ between CPU and RAM
3.
Data bus carries data and ____________
4.
RAM -> data bus -> ___
5.
Writing: MDR -> ____ bus -> RAM

Spot the Error

Shade in the letter of the line that contains an error.

Question 1
A PC -> MAR via address bus
B RAM finds the address
C Data bus carries instruction
D Data bus -> MAR
Question 2
A bus <- 'data bus'
B directions <- 1
C joins <- 'CPU and RAM'
Question 3
A DATA BUS: one-way
B Links CPU and RAM
C Carries data and instructions
D Connects to the MDR
Question 4
A CPU stores a result in RAM
B Result is in the MDR
C Data bus: RAM -> CPU
D RAM saves the value
Question 5
A IF reading from RAM THEN
B data bus: RAM -> CPU
C ELSE
D data bus: not used

Answer Key

Data bus
Section A: Quick Questions
Q1
A — True
Q2
A — Both directions (two-way)
Q3
B — Memory data register (MDR)
Q4
A — False
Q5
B — Data bus
Section B: Match the Pairs
Q1
data bus → A set of wires that carries data and instructions between the CPU and RAM
Q2
MDR <-> Data bus <-> RAM → The data bus works in both directions: the MDR can send data to RAM or receive data from RAM
Q3
The data bus carries instructions as well as data, so a fetched instruction travels along it from RAM to the CPU → RAM --data bus--> MDR (instruction)
Q4
The data bus is two-way, so the CPU can both read from RAM and write to RAM → Read: RAM -> MDR | Write: MDR -> RAM
Q5
The data bus carries only data, never instructions → The data bus carries instructions as well as data. Instructions are fetched from RAM along it into the MDR.
Q6
The data bus is one-way: CPU -> RAM only → The data bus is two-way (bidirectional). It carries values from RAM to the CPU and from the CPU to RAM. Only the address bus is one-way.
Section C: Definitions
Q1
data bus — A set of wires that carries data and instructions in both directions between the CPU and RAM. It connects to the MDR.
Section D: Fill in the Blanks
Q1
The data bus links the CPU and RAM
Q2
Data bus: two-way between CPU and RAM
Q3
Data bus carries data and instructions
Q4
RAM -> data bus -> MDR
Q5
Writing: MDR -> data bus -> RAM
Section E: Spot the Error
Q1
D — The data bus connects to the MDR, not the MAR. The MAR holds addresses and uses the address bus. The line should be Data bus -> MDR.
Q2
B — The data bus is two-way. Data and instructions travel in both directions between the CPU and RAM, so directions should be 2.
Q3
A — The data bus is two-way (bidirectional), not one-way. It should read DATA BUS: two-way.
Q4
C — When the CPU writes a result to RAM, the data bus carries it from the CPU to RAM. The line should be Data bus: CPU -> RAM.
Q5
D — The data bus is used for both reading and writing because it is two-way. When writing, it should be data bus: CPU -> RAM.